View SI8281CD-IS_8654755.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

si8281/82/83/84 data sheet 4.0 amp isodrivers with integrated dc-dc converters the si828x family (si8281/82/83/84) is made up of isolated, high-current gate drivers with integrated system safety and feedback functions. these devices are ideal for driving power mosfets and igbts used in a wide variety of inverter and motor control applica- tions. the si828x isolated gate drivers utilize silicon labs' proprietary silicon isolation technology, supporting up to 5.0 kvrms withstand voltage per ul1577. this technology enables higher-performance, reduced variation with temperature and age, tighter part-to- part matching, and superior common-mode rejection compared to other isolated gate driver technologies. in addition to the gate driver, the si828x family integrates a dc-dc controller for simple implementation of an isolated supply for the driver side. the si828x dc-dc controller can be ordered in two different configurations depending on what system voltage rails are available and the amount of power needed. the si8281 and si8283 have integrated power switch but are limited in dc-dc voltage input to the device bias. the si8282 and si8284 utilize and external power switch and are able to accept much higher voltage in- put power rail. user-adjustable frequency for minimizing emissions, a soft-start function for safety, and a shut-down option are available options. the device requires only mini- mal passive components and a miniature transformer. the input to the device is a complementary digital input that can be utilized in several configurations. the input side of the isolation also has several control and feedback digi- tal signals. the controller to the device receives information about the driver side power state and fault state of the device and recovers the device from fault through an active- low reset pin. on the output side, si828x devices provide separate pull-up and pull-down pins for the gate. a dedicated dsat pin detects the desaturation condition and immediately shuts down the driver in a controlled manner. the si828x devices also integrate a miller clamp to facilitate a strong turn-off of the power switch. applications ? igbt/ mosfet gate drives ? industrial, hev, and renewable energy inverters ? ac, brushless, and dc motor controls and drives ? variable-speed motor controllers ? isolated switch mode and ups power supplies safety regulatory approvals (pending) ? ul 1577 recognized ? up to 5000 v rms for 1 minute ? csa component notice 5a approval ? iec 60950-1, 61010-1, 60601-1 (reinforced insulation) ? vde certification conformity ? iec 60747-5-5/vde0884 part 10 ? cqc certification approval ? gb4943.1 key features ? 4 a igbt driver ? system safety features ? desat detection ? fault feedback ? undervoltage lock out (uvlo) ? soft shutdown on fault condition ? silicon labs high-performance isolation technology ? industry leading noise immunity ? high speed, low latency and skew ? best reliability available ? 30 v driver-side supply voltage ? integrated miller clamp ? power ready pin ? complementary driver control input ? compact packages: 20 and 24-pin wide- body soic ? integrated dc-dc converter ? feedback-controlled converter with dithering for low emi ? dc-dc converter efficiency of 83% ? shutdown, frequency, and soft-start controls ? industrial temp range: C40 to 125 c silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 this information applies to a product under development. its characteristics and specifications are subject to change without notice.
1. ordering guide ordering part number (opn) uvlo voltage dc/dc features package shutdown soft start frequency control external switch si8281bd-is 9 v no no no no wb soic-20 SI8281CD-IS 12 v no no no no wb soic-20 si8282bd-is 9 v no no no yes wb soic-20 si8282cd-is 12 v no no no yes wb soic-20 si8283bd-is (sampling) 9 v yes yes yes no wb soic-24 si8283cd-is (sampling) 12 v yes yes yes no wb soic-24 si8284bd-is (sampling) 9 v yes yes yes yes wb soic-24 si8284cd-is (sampling) 12 v yes yes yes yes wb soic-24 note: add an "r" at the end of the part number to denote tape and reel option. si8281/82/83/84 data sheet ordering guide silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 1
2. system overview 2.1 isolation channel description the operation of an si828x channel is analogous to that of an optocoupler and gate driver, except an rf carrier is modulated instead of light. this simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. a simplified block diagram for a single si828x channel is shown in the figure below. rf oscillator modulator demodulator + noise filter a semiconductor- based isolation barrier transmitter receiver input logic gnd v dd v h v l figure 2.1. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driver. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. 2.2 device behavior the following table shows state relationships for the si828x inputs and outputs. table 2.1. si8281/82/83/84 truth table in+ inC vdda state vddbCvmid state desaturation state vh vl rdy fltb h h powered powered undetected hi-z pull-down h h h l powered powered undetected pull-up hi-z h h l x powered powered undetected hi-z pull-down h h x x powered unpowered l h x x powered powered detected hi-z pull-down 1 h l note: 1. driver state after soft shutdown. si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 2
2.3 input the in+ and inC inputs to the si828x devices act as a complementary pair. if the inC is held low, the in+ will act as a active-high input for the driver control. alternatively, if in+ is held high, then the inC can be used as an active-low input for driver control. when the inC is used as the control signal, taking the in+ low will hold the output driver low. in+ vh _ in vl high low high low pull-up hi-z hi-z pull-down figure 2.2. si828x complementary input diagram 2.4 driver side output the si828x has separate pins for gate drive high (vh) and gate drive low (vl). this makes it simple for the user to use different gate resistors to control igbt v ce rise and fall time. 2.5 fault (fltb) pin fltb is an open-drain type output. once the uvlo condition is cleared on the driver side of the device, the fltb pin is released. a pull-up resistor takes the pin high. when the desaturation condition is detected, the si828x indicates the fault by bringing the fltb pin low. fltb stays low until the controller brings the rstb pin low. fltb is also taken low if the uvlo condition is met during device operation. fltb is released in that case as soon as the uvlo condi- tion is cleared. 2.6 reset (rstb) pin the rstb pin is used to clear the desaturation condition and bring the si828x driver back to an operational state. even though the input may be toggling, the driver will not change state until the fault condition has been reset. 2.7 ready (rdy) pin the ready pin indicates to the controller that power is available on both sides of the isolation, i.e., at vdda and vddb. rdy goes high when both the primary side and secondary side uvlo circuits are disengaged. if the uvlo conditions are met on either side of the isolation barrier, the ready pin will return low. rdy is a push-pull output pin and can be floated if not used. 2.8 undervoltage lockout (uvlo) the uvlo circuit unconditionally drives vl low when vddb is below the lockout threshold. the si828x is maintained in uvlo until vddb rises above vddb uv+ . during power down, the si828x enters uvlo when vddb falls below the uvlo threshold plus hysteresis (i.e., vddb < vddb uv+ C vddb hys ). si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 3
2.9 desaturation detection the si828x provides sufficient voltage and current to drive and keep the igbt in saturation during on time to minimize power dissipa- tion and maintain high efficiency operation. however, abnormal load conditions can force the igbt out of saturation and cause perma- nent damage to the igbt. to protect the igbt during abnormal load conditions, the si828x detects an igbt desaturation condition, shuts down the driver upon detecting a fault, and provides a fault indication to the controller. these integrated features provide desaturation protection with mini- mum external bom cost. the figure below illustrates the si828x desaturation circuit. when the si828x driver output is high, the internal current source is on, and this current flows from the dsat pin to charge the c bl capacitor. the voltage on the dsat pin is monitored by an internal comparator. since the dsat pin is connected to the igbt collector through the d dsat and a small r dsat , its voltage is almost the same as the v ce of the igbt. if the v ce of the igbt does not drop below the si828x desaturation threshold voltage within a certain time after turning on the igbt (blanking period) the block will generate a fault signal. the si828x desaturation hysteresis is fixed at 220 mv and threshold is nominally 7 v. vmid dsat desat sense driver control signal fault signal driver disable c bl r dsa t d dsat 7 v i ch g figure 2.3. desaturation circuit as an additional feature, the block supports a blanking timer function to mask the turn-on transient of the external switching device and avoid unexpected fault signal generation. this function requires an external blanking capacitor, c bl , of typically 390 pf between dsat and vmid pins. the block includes a 1 ma current source (i chg ) to charge the c bl . this current source, the value of the external c bl , and the programmed fault threshold, determine the blanking time (t blanking ). t b l a nk i n g = c b l v de s a t i chg an internal nmos switch is implemented between dsat and vmid to discharge the external blanking capacitor, c bl , and reset the blanking timer. the current limiting r dsat resistor protects the dsat pin from large current flow toward the igbt collector during the igbts body diode freewheeling period (with possible large collectors negative voltage, relative to igbts emitter). 2.10 soft shutdown to avoid excessive dv/dt on the igbts collector during fault shut down, the si828x implements a soft shut down feature to discharge the igbts gate slowly. when soft shut down is activated, the high power driver goes inactive, and a weak pull down via vh and exter- nal rh discharges the gate until the gate voltage level is reduced to the vssb + 2 v level. the high power driver is then turned on to clamp the igbt gate voltage to vmid. after the soft shut down, the si828x driver output voltage is clamped low to keep the igbt in the off state. si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 4
2.11 miller clamp igbt power circuits are commonly connected in a half bridge configuration with the collector of the bottom igbt tied to the emitter of the top igbt. when the upper igbt turns on (while the bottom igbt is in the off state), the voltage on the collector of the bottom igbt flies up sever- al hundred volts quickly (fast dv/dt). this fast dv/dt induces a current across the igbt collector-to-gate capacitor (c cg that constitutes a positive gate voltage spike and can turn on the bottom igbt. this behavior is called miller parasitic turn on and can be destructive to the switch since it causes shoot through current from the rail right across the two igbts to ground. the si828x miller clamps purpose is to clamp the gate of the igbt device being driven by the si828x to prevent igbt turn on due to the collector c cg coupling. r l vl vh driver control r h 2.0 v clmp driver control soft shutdown r ss vssb vssb vssb vddb c cg figure 2.4. miller clamp device the miller clamp device (clamp) is engaged after the main driver had been on (vl) and pulled igbt gate voltage close to vssb, such that one can consider the igbt being already off. this timing prevents the miller clamp from interfering with the drivers operation. the engaging of the miller clamp is done by comparing the igbt gate voltage with a 2.0 v reference (relative to vssb) before turning on the miller clamp nmos. si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 5
2.12 dc-dc converter application information the si828x isolated dc-dc converter is based on a modified fly-back topology and uses an external transformer and rectifying diodes for low cost and high operating efficiency. the pwm controller operates in closed-loop, current mode control and generates isolated output voltages with up to 2 w average output power at vddp = 5.0 v. voltage feedback is referenced between vddb-vssb. although there is only one voltage feedback path, two output voltages are realized by the tight coupling of the two secondary transformer windings. options are available for 24 vdc input operation and externally configured switching frequency. the dc-dc controller modulates a pair of internal, primary-side power switches (see figure 2.5 si8281/83 block diagram: 3 vC5 v input to split voltage output on page 8 ) to generate an isolated voltage at external diode d1 and d2. divider resistors, r1 and r2, gener- ate proper 1.05 v for the vsns pin. closed-loop feedback is provided by an internal compensated error amplifier, which compares the voltage at the vsns pin to an internal voltage reference. the resulting error voltage is fed back across the isolation barrier via an inter- nal feedback path to the controller, thus completing the control loop. for input supply voltages higher than 5 v, an external fet q2 is modulated by a driver pin esw as shown in figure 2.6 si8282/84 block diagram: >5.5 v input to split voltage output on page 9 . a shunt resistor based voltage sense pin, rsn, provides current sensing capability to the controller. the vin must be able to support the si828x vddb-vssd static load current (approximately 9 ma), the output drive load requirement, and the dc-dc power dissipation (loss). the driver power requirement is dependent on the igbt gate charge and the driver switching frequency. below are the equations to calculate the vin power requirement. pv i n = ( 9 10 ? 3 ( v d d b + v s sb ) + q g fs w ) where: qg = igbt total gate charge fsw = driver switching frequency ? = dc-dc efficiency (approximately 78%) additional part number features include an externally-triggered shutdown of the converter functionality using the sh pin and a program- mable soft start configured by a capacitor connected to the ss pin. the resistor value on pin sh/fc and the capacitor value on pin ss are used during power-up to set the dc-dc switching frequency. note that pin sh/fc and ss pins are available on the si8283 and si8284 only. the si828x can be used with a low-voltage power rail or a high-voltage power rail. these features and configurations are explained in more detail in other sections. 2.12.1 external transformer driver the dc-dc controller has internal switches (vsw) for driving the transformer with up to a 5.5 v voltage supply. for higher voltages on the primary side, a driver output (esw) is provided on the si8282 and si8284 that can switch an external nmos power transistor for driving the transformer. when this configuration is used, a shunt resistor based voltage sense pin (rsn) provides current sensing to the controller. 2.12.2 output voltage control the isolated output voltage, vout (vddbCvssb), is sensed by a resistor divider that provides feedback to the controller through the vsns pin. the voltage error is encoded and transmitted back to the primary side controller across the isolation barrier, which in turn changes the duty cycle of the transformer driver. the equation for vout is as follows: v o u t = v s ns ( 1 + r 1 r 2 ) the vddb-vssb voltage split is depended on the ratio of the two secondary windings and can be calculated as follows: vd d b ? v m i d = v o u t ( s 1 s 1 s 2 ) v s s b ? v m id = v o u t ( s 2 s 1 + s 2 ) 2.12.3 compensation the dc-dc converter operates in current mode control. the loop is compensated by connecting an external resistor in series with a ca- pacitor from the comp pin to vssb. the compensation network, rcomp, and ccomp are set to 200 k and 1 nf for most si828x applications. si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 6
2.12.4 thermal protection a thermal shutdown circuit is implemented to protect the system from over-temperature events. the thermal shutdown is activated at a junction temperature that prevents permanent damage from occurring. 2.12.5 cycle skipping cycle skipping is included to reduce switching power losses at light loads. this feature is transparent to the user and is activated auto- matically at light loads. the product options with integrated power switches (si8281/83) may never experience cycle skipping during operation, even at light loads, while the external power switch options (si8282/84) are likely to have cycle skipping start at light loads. 2.12.6 shutdown (si8283 and si8284 only) this feature allows the operation of the dc-dc converter to be shut down when sh/fc is asserted high. this pin normally has a resistor to ground, the value of which is used in conjunction with the value of the capacitor on the ss pin during startup to determine the dc-dc switching frequency. therefore, a gpio pin connected to sh/fc pin to control the shutdown function should be in a high-impedance state during startup to avoid interfering with the internal frequency calculation circuit. during normal operation, this pin should be held low and only taken high to assert dc-dc shutdown. 2.12.7 soft start (si8283 and si8284 only) the dc-dc controller has an internal timer that controls the power conversion start-up to limit inrush current. there is also a soft start option where users can program the soft start up by an external capacitor connected to the ss pin. the soft start period is the maximum duration of time that the si8283/84 will try to ramp up the output voltage. if the output voltage fails to reach the targeted voltage level within this soft start period, the si8283/84 will terminate the dc-dc startup cycle and wait for 40 sec- onds before initiating a new (startup) cycle. the equations for setting the soft start period are as follows: t s s = 200000 c s s or c ss = t ss 200000 2.12.8 programmable frequency (si8283 and si8284 only) the frequency of the pwm modulator is set to a default of 250 khz for si828x. users can program their desired frequency within a given band of 200 khz to 800 khz by controlling the time constant of an external rc connected to the sh_fc and ss pins. the equations for setting f sw or r sw are as follows: f sw = 1025.5 ( r sw c s s ) or r s w = 1025.5 ( f sw c s s ) the following are the recommended steps for calculating c ss and r sw : 1. select the maximum soft start duration (typically 40 ms). 2. calculate css using equation a. 3. select the dc-dc switching frequency. 4. calculate r sw using the above equation. si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 7
2.12.9 low supply voltage configuration the low supply voltage configuration is used when 3.0 v to 5.5 v supply rails are available. all product options of the si8281 and si8283 are intended for this configuration. an advantage of si828x devices over other converters that use this same topology is that the output voltage is sensed on the secon- dary side without requiring additional optocouplers and support circuitry to bias those optocouplers. this allows the dc-dc to operate with superior line and load regulation while reducing external components and increasing lifetime reliability. in a typical isolated gate driver application, the dc-dc powers the si8281 and si8283 vddb and vssb as shown in the figure below. the si8281 and si8283 dc-dc circuit in the figure below can deliver up to 2 w of output power for v in = 5 v and 1 w for v in = 3.3 v. the dc-dc requires an input capacitor, c 2 , blocking capacitor, c 1 , transformer, t 1 , rectifying diodes, d 1 and d 2 , and output capacitors, c 26 , and c 27 . resistors r 1 and r 2 divide the output voltage to match the internal reerence of the error amplifier. the ratio of the two secon- dary windings, s1 and s2, splits the output voltage into two portions. the positive vddb and the negative vssb with common refer- ence to vmid (igbt emitter). v d d b = v o u t ( s 1 s 1 + s 2 ) v s s b = ? v o ut ( s 2 s 1 + s 2 ) type 1 loop compensation made by rcomp and ccomp are required at the comp pin. the combination of rcomp = 200 k and ccomp = 1 nf satisfies most si8281 and si8283 dc-dc applications. though it is not necessary for normal operation, we recommend that an rc snubber (not shown) be placed in parallel with the secondary winding to minimize radiated emissions. rdy /flt vh vl cmos isolation si8281/si8283 freq. control and shutdown soft start uvlo power fet dc-dc controller vsw sh_fc ss vdda css rfsw power fet error amp and compensation encoder uvlo vddb vsns comp vssb r1 vssb vin c 1 t 1 d 1 c 26 hf rx hf tx r2 c 2 rcomp ccomp dsat detection hf rx driver miller clamp clmp dsat vmid hf tx decoder encoder decoder /rst +in -in input control & reset d 2 c 27 vddp s1 s2 vmid figure 2.5. si8281/83 block diagram: 3 vC5 v input to split voltage output 2.12.10 high supply voltage configuration 2h =.w..]6+*28x9q\\- si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 8
the high supply voltage configuration is used when a higher voltage power supply rail (up to 24 v) is available. all product options of the si8282 and si8284 are intended for this configuration. the dc-dc converter uses the isolated flyback topology. with this topology, the switch and sense resistor are external, allowing higher switching voltages. the output voltage is sensed on the secondary side without requiring additional optocouplers and support circuitry to bias those opto- couplers. this allows the dc-dc to operate with superior line and load regulation. the figure below shows the block diagram of an si828x with external components. the si8284 product option has externally controlled switching frequency and soft start. the dc-dc requires input capacitor c 28 , transformer t 1 , switch q 4 , sense resistor r sense , rectifying diodes d 1 and d 2 , and output capacitors c 26 and c 27 . to supply vdda, q 3 transistor is biased by r 23 , 5.6 v zener diode d 5 and filtered by c 30 and c 11 . external frequency and soft start behavior is set by css and rfsw. resistors r 1 and r 2 divide the output voltage to match the internal reference of the error amplifier. the ratio of the two secondary windings splits the output voltage into two portions. the positive vddb and the negative vssb with common reference to vmid (igbt emitter). v d d b = v o u t ( s 1 s 1 + s 2 ) v s s b = ? v o ut ( s 2 s 1 + s 2 ) type 1 loop compensation made by rcomp and ccomp are required at the comp pin. the combination of rcomp = 49.9 k and ccomp = 1.5 nf satisfies most si8282 and si8284 dc-dc applications. though it is not necessary for normal operation, we recommend to use rc snubbers (not shown) on both primary and secondary windings to minimize high-frequency emissions. rdy /flt vh vl cmos isolation si8282/si8284 error amp and compensation encoder uvlo vddb vsns comp vssb r1 vssb vin t 1 d 1 c 26 hf rx hf tx r 2 c 28 rcomp ccomp dsat detection hf rx driver miller clamp clmp dsat vmid hf tx decoder encoder decoder /rst +in -in input control & reset d 2 c 27 freq. control and shutdown soft start dc-dc controller current sensing uvlo fet driver esw vdda rsn gndp rsense r 23 q 4 q 3 fc_sh ss css rfsw 5.6v c 1 1 c 30 d 5 figure 2.6. si8282/84 block diagram: >5.5 v input to split voltage output si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 9
2.13 transformer design the internal switch dc-dc (si8281, si8283) and external switch dc-dc (si8282, si8284) operate in different topologies and, thus, require different transformer designs. the table below provides a list of transformers and their parametric characteristics that have been valida- ted to work with si828x products. it is recommended that users order the transformers from the vendors per the part numbers given below. to manufacture transformers from your preferred suppliers that may not be listed below, please specify to supplier the parametric char- acteristics as specified in the table below for a given input voltage and isolation rating. table 2.2. si828x recommended transformers transformer supplier ordering part # input voltage turns ratio leakage inductance primary inductance primary resistance isolation rating umec www.umec-usa.com utb02257s 3.0C5.5 v 1:15:5 125 nh max 1.5 h 5% 0.05 max 5 kv utb02241s 4.5C5.5 v 1:9:33.667 100 nh max 2 h 5% 0.05 max 5 kv utb02253s 7C24 v 1.2:1.21 200 nh max 25 h 5% 0.225 max 5 kv coilcraft www.coilcraft.com ta7788-al 7C24 v 1:1.25:0.75 550 nh max 25 h 5% 0.460 max 5 kv si8281/82/83/84 data sheet system overview silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 10
3. applications information the following sections detail the input and output circuits necessary for proper operation. 3.1 recommended application circuits css rsw c26 10uf c27 10uf t1 lp 3 8 6 5 2 7 d1 b160 d2 b160 r13 100 c2 100pf r2 r1 q1 mcu 0.1uf rc 200k cc 1nf cbl c1 10uf c7 10uf c8 0.1uf q2 dsat 0.1uf 10uf rdsat + rail - rail place rdsat, dsat, cbl as close to q1 as possible si8281/83 vdda vh clmp vsw gndp nc vddp dsat vsns ss gnda vddb sh/fc /rst comp vl /flt rdy/ssh vmid vssb in+ in- vssb nc vin rh rl 0.1uf 10uf rfc, css, pin sh/fc, ss are available on si8283 only s1 s2 vddb vssb 220nf vin 10k 10k 100pf 100 100pf 100pf r8 r9 r7 c12 c13 c14 c15 c20 c21 c22 figure 3.1. recommended si8281/83 application circuit si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 11
c28 10uf q3 mmbt2222lt1 vdda vin the components in this box can be removed if 5v source is available to connect to the vdda directly r14 = (vin C 5.6)/0.001 vin = 7v to 24v auxiliary vddp to 5v vdda circuit c11 0.1uf c13 0.1uf rsense 0.1 r23 15k d5 5.6v r22 10.0 c30 0.1uf q4 fdt3612 r1 rdsat rl cc 1nf r2 0.1uf rsw rc 200k mcu d1 b160 css c2 100pf dsat r13 100 d2 b160 c27 10uf 10uf 10uf c26 10uf cbl q2 q1 0.1uf rh + rail - rail place rdsat, ddsat, and cbl as close to q1 as possible t1 25uh 2 8 6 5 3 7 r24 100 c31 100pf si8282/84 vdda vh clmp rsn gndp nc esw dsat vsns ss gnda vddb sh/fc /rst comp vl /flt rdy vmid vssb in+ in- vssb nc rfc, css, pin sh/fc, ss are available on si8284 only s1 s2 vddb vssb 220nf vin 10k 10k 100pf 100 100pf 100pf r8 r9 r7 c20 c21 c22 c12 c13 c14 c15 figure 3.2. recommended si8282/84 application circuit the si828x has both inverting and non-inverting gate control inputs (inC and in+). in normal operation, one of the inputs is not used, and should be connected to gnda (inC) or vdda (in+) for proper logic termination. the si828x has an active low reset input (rstb), an active high ready (rdy) push pull output, and an open drain fault (fltb) output that requires a weak 10 k pull-up resistor. the si828x gate driver will shut down when a fault is detected. it then provides fltb indication to the mcu, and remains in the shutdown state until the mcu applies a reset signal. the desaturation sensing circuit consisted of the 380 pf blanking capacitor, 100 current limiting resistor, and dsat diode. these components provide current and voltage protection for the si828x desaturation dsat pin and it is critical to place these components as close to the igbt as possible. also, on the layout, make sure that the loop area forming between these components and the igbt be minimized for optimum desaturation detection. the si828x has vh and vl gate drive outputs with external rh and rl resistors to limit output gate current. the value of these resistors can be adjusted to independently control igbt collector voltage rise and fall time. the clmp output should be connected to the gate of the igbt directly to provide clamping action between the gate and vssb. this clamp- ing action dissipates igbt miller current from collector to the gate to secure the igbt in the off-state. 3.1.1 inputs inputs should be driven by cmos level push-pull output. if input is driven by the mcu gpio, it is recommended that the mcu be loca- ted as closed to the si828x as possible to minimize pcb trace parasitic and noise coupling to the input circuit. in noisy environments, it is customary to add a small series resistor, and a decoupling cap to the in traces (r7, c20 in figure 3.1 recommended si8281/83 application circuit on page 11 and figure 3.2 recommended si8282/84 application circuit on page 12 ). these rc filters attenuate glitches from electrical noise and improve input-to-output signal integrity. si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 12
3.1.2 reset, rdy, and fault the si828x has an active high ready (rdy) push pull output, an open drain fault (fltb) output, and an active low reset input (rstb) that require pull-up resistors (r8 and r9). fast common-mode transients in high-power circuits can inject noise and glitches into these pins due to parasitic coupling. depending on the igbt power circuit layout, additional capacitance (use 100 pf to 470 pf for c21 and c22) can be included on these pins to prevent faulty rdy and fltb indications as well as unintended reset to the device. the fltb outputs from multiple si828x devices can be connected in an or wiring configuration to provide a single fltb signal to the mcu. 3.1.3 desaturation the desaturation sensing circuit consists of the blanking capacitor (390 pf recommended), 100 current limiting resistor, and dsat diode. these components provide current and voltage protection for the si828x desaturation dsat pin, and it is critical to place these components as close to the igbt as possible. also, in the layout, the loop area forming between these components and the igbt should be minimized for optimum desaturation detection. 3.1.4 driver outputs the si828x has vh and vl gate drive outputs (see figure 3.1 recommended si8281/83 application circuit on page 11 ). they work with external rh and rl resistors to limit output gate current. the value of these resistors can be adjusted to independently control igbt collector voltage rise and fall time. the clmp output should be connected to the gate of the igbt directly to provide clamping action between the gate and vssb pin. this clamping action dissipates igbt miller current from the collector to the gate to secure the igbt in the off-state. negative vssb pro- vides further help to ensure the gate voltage stays below the igbts vth during the off state. 3.2 layout considerations it is most important to minimize ringing in the drive path and noise on the supply lines. care must be taken to minimize parasitic induc- tance in these paths by locating the si828x as close as possible to the device it is driving. in addition, the supply and ground trace paths must be kept short. for this reason, the use of power and ground planes is highly recommended. a split ground plane system having separate ground and power planes for power devices and small signal components provides the best overall noise performance. si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 13
3.3 power dissipation considerations proper system design must assure that the si828x operates within safe thermal limits across the entire load range. the si828x total power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by the series gate resistor and load. equation 1 shows total si828x power dissipation. pd = ( v d d a ) ( i d d a ) + 1.05 ( v d d b )( i d d b ) + 1.05 f q int vddb + 1.05 2 ( f )( q ig bt ) (v ddb ) rp rp + rh + rn rn + rl where: pd is the total si828x device power dissipation (w). idda is the input-side maximum bias current (7.5 ma). iddb is the driver die maximum bias current (10.8 ma). q int is the internal parasitic charge (3 nc). vdda is the input-side vdd supply voltage (2.7 to 5.5 v). vddb is the total driver-side supply voltage (vddb + vssb: 12.5 to 30 v). f is the igbt switching frequency (hz). rh is the vh external gate resistor, rl is the vl external gate resistor. rp is the rds (on) of the driver pull-up switch: (2.6 ). rn is the rds (on) of the driver pull-down switch: (0.8 ). equation 1. to account for the si828x dc-dc loss, an additional 5% of power is added to the driver-side circuit (vddb). the maximum power dissi- pation allowable for the si828x is a function of the package thermal resistance, ambient temperature, and maximum allowable junction temperature, as shown in equation 2: pd max tj max ? ta j a where: pdmax = maximum si828x power dissipation (w). tjmax = si828x maximum junction temperature (150 c). ta = ambient temperature (c) ja = si828x junction-to-air thermal resistance (60 c/w for four-layer pcb) f = si828x switching frequency (hz) equation 2. substituting values for pdmax tjmax (150 c), ta (125 c), and ja (60 c/w) into equation 2 results in a maximum allowable total power dissipation of 0.42 w. pd max 150 ? 125 60 = 0.42 w si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 14
maximum allowable load is found by substituting this limit and the appropriate data sheet values from table 4.1 into equation 1 and simplifying. the result is equation 3. pd = ( v d d a ) ( i d d a ) + 1.05 ( v d d b ) ( id db ) + 1.05 f q int vddb + 1.05 2 ( f )( q l ) (v ddb ) rp rp + rh + rn rn + rl pd = ( v d d a ) ( i d d a ) + 1.05 (v d db )( i d d b ) + 1.05 f q int vddb + 1.05 2 ( f )( c l )( vddb 2 ) rp rp + rh + rn rn + rl 0.42 = ( vd d a) ( 0.0075) + 1.05 ( vdd b ) ( 0.0108 ) + 1.05 f 3 10 ? 9 vddb + 1.05 2 ( f )( c l )( vddb 2 ) 2.6 2.6 + 15 + 0.8 0.8 + 10 0.42 ? (v d d a ) ( 0.0075) ? 1.05( vddb )(0.0108) ? 1.05 f 3 10 ? 9 vddb = 0.117 vddb 2 f ( c l ) c l = 0.42 ? ( v d d a 7.5 10 ? 3 ) ? ( vddb 10.8 10 ? 3 ) 0.117 vddb 2 ( f ) ? 2.692 10 ? 8 vddb equation 3. below is an example power dissipation calculation for the si828x driver using equation 1 with the following givens: v dda = 5.0 v v ddb = 18 v f = 30 khz r h = 10 r l = 15 q g = 85 nc p d = ( 5 ) ( 0.0075 ) + 1.05 ( 18) ( 0.0108 ) + 1.05 ( 2 10 4 )( 3 10 ? 9 ) (18) + 1.05 2 ( 3 10 4 )( 85 10 ? 9 )( 18 ) 2.6 2.6 + 10 + 0.8 0.8 + 15 = 242 mw the driver junction temperature is calculated using equation 2, where: pd is the total si828x device power dissipation (w) ja is the thermal resistance from junction to air (60 c/w in this example) ta is the maximum ambient temperature (125 c) t j = pd j a + t a tj = ( 0.242 ) ( 60) + 125 = 139.5 c calculate maximum loading capacitance from equation 3: 1. vdda = 5 v and (vddbCvssb) = 12.5 v. c l = 1.51 10 ? 2 f ? 2.15 10 ? 9 2. vdda = 5 v and (vddbCvssb) = 18 v. c l = 5.91 10 ? 3 f ? 1.5 10 ? 9 3. vdda = 5 v and (vddbCvssb) = 30 v. c l = 1.04 10 ? 3 f ? 8.97 10 ? 10 graphs are shown in the following figure. all points along the load lines in these graphs represent the package dissipation-limited value of c l for the corresponding switching frequency. si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 15
figure 3.3. maximum load vs. switching frequency (25 c) si8281/82/83/84 data sheet applications information silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 16
4. electrical specifications table 4.1. electrical specifications v in = 24 v; v dda = 4.3 v (see figure 3) for all si8282/84; v dda = v ddp = 3.0 to 5.0 v (see figure 2) for all si8281/83; t a = C40 to +125 c unless otherwise noted. parameter symbol test condition min typ max units dc parameters input supply voltage vdda 2.8 5.5 v power input voltage vddp 3.0 5.5 v driver supply voltage (vddb C vssb) 9.5 30 v (vmid C vssb) 0 15 v input supply quiescent current idda(q) 6.8 7.5 ma input supply active current idda f = 10 khz 10.5 ma output supply quiescent current iddb(q) 8.7 10.8 ma dc-dc converter switching frequency si8281, si8282 fsw 250 khz switching frequency si8283, si8284 fsw rfsw = 23.3 k fsw = 1025.5/(rfsw x css) css = 220 nf (1% tolerance on bom) 180 200 220 khz rfsw = 9.3 k fsw = 1025.5/(rfsw x css) css = 220 nf (1% tolerance on bom) 450 500 550 khz rfsw = 5.18 k css = 220 nf 810 900 990 khz vsns voltage vsns iload = 0 a 1.002 1.05 1.097 v vsns current offset i offset C500 500 na output voltage accuracy iload = 0 ma C5 +5 % line regulation vout(line)/ vddp iload = 50 ma vddp varies from 4.5 to 5.5 v 1 mv/v load regulation vout(load)/ vout iload = 50 to 400 ma 0.1 % output voltage ripple si8281, si8283 si8282, si8284 iload = 100 ma 100 mv p-p turn-on overshoot vout(start) cin = cout = 0.1 f in paral- lel with 10 f iload = 0 a 2 % si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 17
parameter symbol test condition min typ max units continuous output current si8281, si8283 5.0 v to 5.0 v 3.3 v to 3.3 v 3.3 v to 5.0 v si8282, si8284 24 v to 5.0 v 24 v to 3.0 v iload(max) 200 400 250 1000 1500 ma cycle-by-cycle average current limit si8281, si8283 ilim output short circuited 3 a no-load supply current iddp si8281, si8283 iddpq_dcdc vddp = vdda = 5 v 30 ma no-load supply current idda si8281, si8283 iddaq_dcdc vddp = vdda = 5 v 5.7 ma no-load supply current iddp si8282, si8284 iddpq_dcdc vin = 24 v 0.8 ma no-load supply current idda si8282, si8284 iddaq_dcdc vin = 24 v 5.8 ma peak efficiency si8281, si8283 si8282, si8284 78 83 % soft start time, full load si8281, si8282 si8283, si8284 t sst 25 50 ms restart delay from fault event t otp 21 s drive parameters high drive transistor rds(on) r oh 2.48 low drive transistor rds(on) r ol 0.86 high drive peak output current i oh vh = vddb C 15 v t pw_ioh < 250 ns 2.5 2.8 a low drive peak output current i ol vl = vssb + 6.0 v t pw_iol < 250 ns 3.0 3.4 a uvlo parameters uvlo threshold + vdda uv+ 2.4 2.7 3.0 uvlo threshold C vdda uvC 2.3 2.6 2.9 uvlo lockout hysteresisC (input side) vdda hys 100 mv si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 18
parameter symbol test condition min typ max units uvlo threshold + (driver side) 9 v threshold (si828xbd) 12 v threshold (si828xcd) vddb uv+ 8.0 10.8 9.0 12.0 10.0 13.2 v v uvlo threshold C (driver side) 9 v threshold (si828xbd) 12 v threshold (si828xcd) vddb uvC 7.0 9.8 8.0 11.0 9.0 12.2 v v uvlo lockout hysteresis (driver side) vddb hys 1 v uvlo+ to rdy high delay t uvlo+ to rdy 100 s ulvoC to rdy low delay t uvloC to rdy 0.79 s desaturation detector parameters desat threshold vdesat vddb C vssb > vddbuv+ 6.5 6.9 7.3 v c bl charging current i chg 1 ma desat sense to 90% vout delay t desat(90%) 220 300 ns desat sense to 10% vout delay t desat(10%) 0.77 2.5 2.7 s desat sense to flt low delay t desat to flt 220 300 ns reset to flt high delay t rst to flt 37 45 ns miller clamp parameters (si8285 only) clamp pin threshold voltage v t clamp 2.0 v miller clamp transistor rds (on) r mc 1.07 clamp low level sinking current i cl vclmp = vssb + 6.0 3.0 3.4 a digital parameters logic high input threshold vih 2.0 v logic low input threshold vil 0.8 v input hysteresis vihyst 440 mv high level output voltage (rdy pin on- ly) voh io = C4 ma vdda C 0.4 v low level output voltage (rdy pin on- ly) vol io = 4 ma 0.4 v open-drain low level output voltage (flt pin only) vdda = 5 v, 5 k pull-up resistor 200 mv ac switching parameters propagation delay (low-to-high) t plh cl = 200 pf 30 40 50 ns propagation delay (high-to-low) t phl cl = 200 pf 30 40 50 ns pulse width distortion pwd |t plh C t phl | 1 5 ns propagation delay difference 4 pdd t phlmax C t plhmin C1 25 ns rise time t r cl = 200 pf 5.5 15 ns si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 19
parameter symbol test condition min typ max units fall time t f cl = 200 pf 8.5 20 ns common mode transient immunity output = low or high (vcm = 1500 v) 35 50 kv/s 1. see ordering guide for more information. 2. minimum value of (vdd C gnd) decoupling capacitor is 1 f. 3. when performing this test, it is recommended that the dut be soldered to avoid trace inductances, which may cause overstress conditions. 4. guaranteed by characterization. 10 f 10 f t1 b160 100 100 pf utb02174s i ddb vsw vddp vdda sh gnda gndp vssb comp vsns vddb isolation 200 k 1 nf 7.87 k 182 k 10 f + _ + _ 10 f vmid b160 i out i in v out v in i ddp i dda figure 4.1. si8281, si8283 measurement circuit for converter efficiency and regulation si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 20
+ _ 10 f isolation utb02246s t1 i ddb fdt3612 15 k mmbt2222lt1 0.1 182 k 8.66 k 200 k 1 nf 0.1 f 18.7 k 0.22 f gnda sh_fc ss vdda gndp rsns esw vmid vsns comp vssb 100 100pf 0.1 f 100 100 pf 10 f v out + _ 10 f b160 vddb bzt52c5v6s-f-7 b160 i out i ddp i in i dda v in figure 4.2. si8282, si8284 measurement circuit for converter efficiency and regulation figure 4.3. common-mode transient immunity characterization circuit si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 21
table 4.2. absolute maximum ratings 1 parameter symbol min max unit storage temperature t stg C65 +150 c operating temperature t a C40 +125 c junction temperature t j +140 c peak output current (t pw = 10 s) i opk 4.0 a supply voltage vdd C0.5 36 v output voltage v out C0.5 36 v input power dissipation p i 100 mw output power dissipation p o 800 mw total power dissipation (all packages limited by thermal derating curve) p t 900 mw lead solder temperature (10 s) 260 c hbm rating esd 4 kv machine model esd 300 v cdm 2000 v maximum isolation (input to output) (1 sec) wb soic-16 6500 v rms note: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for ex- tended periods may affect device reliability. si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 22
4.1 timing diagrams uvlo threshold - vdda gnda uvlo threshold + t uvlo- to rdy t uvlo+ to rdy rdy vddb - vmid figure 4.4. uvlo condition to rdy output dsat vh vl v desat vssb + 2 v t flt t dsa t t o ss t /rst-flt rst flt figure 4.5. device reaction to desaturation event si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 23
4.2 typical operating characteristics si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 24
si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 25
si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 26
si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 27
4.3 regulatory information table 4.3. regulatory information 1, 2 csa the si828x is certified under csa component acceptance notice 5a. for more details, see file 232873. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. vde the si828x is certified according to vde0884. for more details, see file 5006301-4880-0001. vde 0884-10: up to 1414 v peak for reinforced insulation working voltage. ul the si828x is certified under ul1577 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. cqc the si828x is certified under gb4943.1-2011. rated up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working voltage. note: 1. regulatory certifications apply to 5.0 kv rms rated devices, which are production tested to 6.0 kv rms for 1 sec. 2. for more information, see 1. ordering guide . table 4.4. insulation and safety-related specifications parameter symbol test condition value unit wb soic nominal air gap (clearance) 1 l(1o1) 8.0 mm nominal external tracking (creepage) l(1o2) 8.0 mm minimum internal gap (internal clearance) 0.016 mm tracking resistance (proof tracking index) pti iec60112 600 v erosion depth ed 0.019 mm resistance (input-output) 2 r io 10 12 capacitance (input-output) 2 c io f = 1 mhz 1 pf note: 1. the values in this table correspond to the nominal creepage and clearance values as detailed in 6.1 package outline: 20-pin wide body soic and 6.3 package outline: 24-pin wide body soic . vde certifies the clearance and creepage limits as 8.5 mm minimum for the wb soic-16. ul does not impose a clearance and creepage minimum for component level certifications. csa certifies the clearance and creepage limits as 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si828x is converted into a 2-terminal device. pins 1C8 are shorted together to form the first terminal, and pins 9C16 are shorted together to form the second terminal. the parameters are then measured between these two terminals. si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 28
table 4.5. iec 60664-1 ratings parameter test condition specification wb soic basic isolation group material group i installation classification rated mains voltages 150 v rms i-iv rated mains voltages 300 v rms i-iv rated mains voltages 600 v rms i-iii table 4.6. iec 60747-5-5 (vde 0884 part 10) insulation characteristics 1 parameter symbol test condition characteristic unit wb soic maximum working insulation voltage v iorm 1414 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m = 1 sec, partial dis- charge < 5 pc) 2652 v peak transient overvoltage v iotm t = 60 sec 8000 v peak surge voltage v iosm tested per iec 60065 with surge voltage of 1.2 s/50 s with magnitude 6250 v x 1.6 = 10 kv 6250 kv peak pollution degree (din vde 0110, see ta- ble xx.) 2 insulation resistance at t s , v io = 500 v r s >10 9 note: 1. this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensur- ed by protective circuits. the si828x provides a climate classification of 40/125/21. table 4.7. iec safety limiting values 1 parameter symbol test condition max unit wb soic-20 wb soic-24 case temperature t s 150 150 c input current i s ja = 60 c/w (wb soic-20 or soic-24) t j = 140 c, t a = 25 c 30 30 ma output power p s 0.9 0.9 w note: 1. maximum value allowed in the event of a failure. si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 29
table 4.8. thermal characteristics parameter symbol typ unit wb soic-20 wb soic-24 ic junction-to-air thermal resistance ja 60 60 c/w si8281/82/83/84 data sheet electrical specifications silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 30
5. pin descriptions si8281 gndp vsw vsns comp nc dsat vddb vh vl clmp vddp vdda gnda rst flt rdy in+ in _ vmid vssb si8282 gndp rsn vsns comp nc dsat vddb vh vl clmp esw vdda gnda rst flt rdy in+ in _ vmid vssb table 5.1. si8281/82 pin descriptions name si8281 pin # si8282 pin # description gndp 1 1 power stage ground vsw 2 power stage internal switch rsn 2 power stage current sense vddp 3 power stage supply esw 3 power stage external switch drive vdda 4 4 input side low voltage power supply gnda 5 5 input side low voltage ground rstb 6 6 reset fault condition fltb 7 7 fault condition signal rdy 8 8 uvlo ready signal in+ 9 9 driver control plus inC 10 10 driver control minus vssb 11 11 output side low voltage power supply vmid 12 12 drain reference for driven switch clmp 13 13 miller clamp vl 14 14 low gate drive vh 15 15 high gate drive vddb 16 16 output side low voltage power supply dsat 17 17 desaturation detection input nc 1 18 18 no connect comp 19 19 dc/dc compensation vsns 20 20 dc/dc voltage feedback note: 1. no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. si8281/82/83/84 data sheet pin descriptions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 31
si8283 gndp vsw vsns comp nc dsat vddb vh vl clmp vddp vdda sh/fc rst flt rdy in+ in _ vmid vssb ss gnda nc vssb si8284 gndp rsn vsns comp nc dsat vddb vh vl clmp esw vdda sh/fc rst flt rdy in+ in _ vmid vssb ss gnda nc vssb table 5.2. si8283/84 pin descriptions name si8283 pin # si8284 pin # description gndp 1 1 power stage ground vsw 2 power stage internal switch rsn 2 power stage current sense vddp 3 power stage supply esw 3 power stage external switch drive vdda 4 4 input side low voltage power supply sh/fc 5 5 shutdown and switch frequency control ss 6 6 soft startup control gnda 7 7 input side low voltage ground rstb 8 8 reset fault condition fltb 9 9 fault condition signal rdy 10 10 uvlo ready signal in+ 11 11 driver control plus inC 12 12 driver control minus vssb 13, 15 13, 15 output side low voltage power supply vmid 16 16 drain reference for driven switch clmp 17 17 miller clamp vl 18 18 low gate drive vh 19 19 high gate drive vddb 20 20 output side low voltage power supply dsat 21 21 desaturation detection input nc 1 14, 22 14, 22 no connect comp 23 23 dc/dc compensation vsns 24 24 dc/dc voltage feedback note: 1. no connect. these pins are not internally connected. to maximize cmti performance, these pins should be connected to the ground plane. si8281/82/83/84 data sheet pin descriptions silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 32
6. packaging 6.1 package outline: 20-pin wide body soic the figure below illustrates the package details for the si8281/82 in a 20-pin wide body soic. the table lists the values for the dimen- sions shown in the illustration. figure 6.1. 20-pin wide body soic symbol millimeters min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 12.80 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 8 si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 33
symbol millimeters min max aaa 0.10 bbb 0.33 ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation ac. 4. recommended reflow profile per jedec j-std-020c specification for small body, lead-free components. si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 34
6.2 land pattern: 20-pin wide body soic the figure below illustrates the recommended land pattern details for the si8281/2 in a 20-pin wide body soic. the table lists the values for the dimensions shown in the illustration. figure 6.2. pcb land pattern: 20-pin wide body soic table 6.1. 20-pin wide body soic land pattern dimensions 1, 2 dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 note: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc), and a card fabrication tolerance of 0.05 mm is assumed. si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 35
6.3 package outline: 24-pin wide body soic the figure below illustrates the package details for the si8283/4 in a 24-pin wide body soic. the table lists the values for the dimen- sions shown in the illustration. figure 6.3. 24-pin wide body soic symbol millimeters min max a 2.65 a1 0.10 0.30 a2 2.05 b 0.31 0.51 c 0.20 0.33 d 15.40 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 0 8 aaa 0.10 bbb 0.33 si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 36
symbol millimeters min max ccc 0.10 ddd 0.25 eee 0.10 fff 0.20 note: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation ad. 4. recommended reflow profile per jedec j-std-020 specification for small body, lead-free components. si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 37
6.4 land pattern: 24-pin wide body soic the figure below illustrates the recommended land pattern details for the si8283/4 in a 24-pin wide body soic. the table lists the values for the dimensions shown in the illustration. figure 6.4. pcb land pattern: 24-pin wide body soic table 6.2. 24-pin wide body soic land pattern dimensions 1, 2 dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 note: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc), and a card fabrication tolerance of 0.05 mm is assumed. si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 38
6.5 top marking: 20-pin and 24-pin wide body soic si828xuv yywwrttttt tw si828xuv yywwrttttt tw e4 si8281/82 top marking si8283/84 top marking table 6.3. si8281/2/3/4 top marking explanation line 1 marking: customer part number si8281, si8282, si8283, si8284 = isodriver u = uvlo level: b = 9 v; c = 12 v v = isolation rating: d = 5.0 kv line 2 marking: rttttt = mfg code manufacturing code from the assembly purchase order form r indicates revision line 3 marking: circle = 43 mils diameter left-justified "e4" = pb-free symbol yy = year ww = workweek assigned by the assembly house. corresponds to the year and workweek of the mold date. si8281/82/83/84 data sheet packaging silabs.com | smart. connected. energy-friendly. preliminary rev. 0.5 | 39
table of contents 1. ordering guide .............................. 1 2. system overview .............................. 2 2.1 isolation channel description ........................2 2.2 device behavior .............................2 2.3 input .................................3 2.4 driver side output ............................3 2.5 fault (fltb) pin .............................3 2.6 reset (rstb) pin .............................3 2.7 ready (rdy) pin .............................3 2.8 undervoltage lockout (uvlo) ........................3 2.9 desaturation detection ...........................4 2.10 soft shutdown .............................4 2.11 miller clamp ..............................5 2.12 dc-dc converter application information ....................6 2.12.1 external transformer driver ........................6 2.12.2 output voltage control ..........................6 2.12.3 compensation .............................6 2.12.4 thermal protection ...........................7 2.12.5 cycle skipping ............................7 2.12.6 shutdown (si8283 and si8284 only) .....................7 2.12.7 soft start (si8283 and si8284 only) .....................7 2.12.8 programmable frequency (si8283 and si8284 only) ...............7 2.12.9 low supply voltage configuration ......................8 2.12.10 high supply voltage configuration .....................8 2.13 transformer design ........................... 10 3. applications information .......................... 11 3.1 recommended application circuits ....................... 11 3.1.1 inputs ................................ 12 3.1.2 reset, rdy, and fault .......................... 13 3.1.3 desaturation .............................. 13 3.1.4 driver outputs ............................. 13 3.2 layout considerations ........................... 13 3.3 power dissipation considerations ....................... 14 4. electrical specifications .......................... 17 4.1 timing diagrams ............................. 23 4.2 typical operating characteristics ....................... 24 4.3 regulatory information ........................... 28 5. pin descriptions ............................. 31 table of contents 40
6. packaging ............................... 33 6.1 package outline: 20-pin wide body soic .................... 33 6.2 land pattern: 20-pin wide body soic ..................... 35 6.3 package outline: 24-pin wide body soic .................... 36 6.4 land pattern: 24-pin wide body soic ..................... 38 6.5 top marking: 20-pin and 24-pin wide body soic .................. 39 table of contents 41
http://www.silabs.com silicon laboratories inc. 400 west cesar chavez austin, tx 78701 usa smart. connected. energy-friendly products www.silabs.com/products quality www.silabs.com/quality support and community community.silabs.com disclaimer silicon labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the silicon labs products. characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "typical" parameters provided can and do vary in different applications. application examples described herein are for illustrative purposes only. silicon labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. silicon labs shall have no liability for the consequences of use of the information supplied herein. this document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. the products are not designed or authorized to be used within any life support system without the specific written consent of silicon labs. a "life support system" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. silicon labs products are not designed or authorized for military applications. silicon labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons. trademark information silicon laboratories inc.? , silicon laboratories?, silicon labs?, silabs? and the silicon labs logo?, bluegiga?, bluegiga logo?, clockbuilder?, cmems?, dspll?, efm?, efm32?, efr, ember?, energy micro, energy micro logo and combinations thereof, "the worlds most energy friendly microcontrollers", ember?, ezlink?, ezradio?, ezradiopro?, gecko?, isomodem?, precision32?, proslic?, simplicity studio?, siphy?, telegesis, the telegesis logo?, usbxpress? and others are trademarks or registered trademarks of silicon labs. arm, cortex, cortex-m3 and thumb are trademarks or registered trademarks of arm holdings. keil is a registered trademark of arm limited. all other products or brand names mentioned herein are trademarks of their respective holders.

▲Up To Search▲

Price & Availability of SI8281CD-IS

	To Download SI8281CD-IS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .